Impementing a 1 bit equality comparator in an FPGA

FPGAs(Field programmable gate arrays) are chips that can implement digital logic in  their fabric and are very useful in in a few use cases where CPUs fall behind such as:

  • implementing custom/rare protocols. Example: You can take an FPGA to interface to a communication bus in a device that has a rare protocol.
  • Building high speed communication interfaces such as optical transceivers for fiber communication as an example.
  • Implementing parallel, Digital signal processing(DSP) algorithms/calculations such as Fast Fast Fourier transforms(FFT) and more.
  • High speed IO
  • Among Others

An FPGAs main strength is in its versatility. One can even build a custom CPU/architecture with an FPGA.


I am in this example going to implement a 1 bit comparator and test using the Numato elbert V2 from Numato labs. It is open source, at least for the design and at 30 dollars, it is  thus very cheap and uses a Xilinx spartan 3A FPGA FROM Xilinx. The spartan3A FPGA isn’t cutting edge but it gets the job done, in fact it is nearing obsolescence in its product life cycle(PDF warning).

A tutorial of how to set up the Elbert is outside this scope but can be found here .My language of choice is verilog.

The digital equality comparator

A digital comparator is a device/unit that compares which signal amongst its digital inputs is greater. This is different from an analogue comparator. For a 2 input equality comparator , this compares whether the 2 signal at the inputs are at the same logic level per clock cycle.

The diagram below from my oscilloscope shows that at any one time the logic level of the 2 signals are always equal therefore at any one given time the logic levels are both either high(peaks), corresponding to a high voltage, or low(troughs),corresponding to a low voltage.


Oscilloscope vertical axis units: Voltage

Oscilloscope horizontal axis units: Time

One can do the same on a micro-controller but this may take 3-5 instructions and with each instruction taking probably 2 clock cycles, depending on the device, thus the entire operation takes 6-10 clock cycles. For an FPGA, the entire operation should take under 1 system clock cycle.

As opposed to writing code that goes into a micro controller for execution, an FPGA has no code. An FPGA contains logic gates for simpler FPGAs while more capable FPGAs may have extra integrated peripherals(IPs) such as Gigabit transceivers for communications, whole CPUs , DDRX RAM controllers among others.

FPGAs get grouped by the manufacturer by families. For example spartan 3 and spartan 6 are different families from Xilinx, but say within, the spartan 3 family, one can have various products that are optimized for various markets. Example, in the spartan 3 family we have various spartan 3 devices optimised for various markets as below:


Image copyright Xilinx

When you program an FPGA, thus there is no code. All you are doing is arranging the logic gates and integrated peripherals to give you a certain behavior. This process is called configuration.

When an FPGA boots up, it is nothing but a “sea” of logic gates. It thus looks for a connected flash rom or a supported storage peripheral where it an load configuration code that instructs it how to arrange its gates and integrated peripherals ON boot. FPGAs thus are volatile due to this fact.

My Workflow

  • Form the comparator truth table
  • Derive by hand the SOP(sum of products) and POS(products of sums) equation from the truth table.
  • Implement the logic on a computer using the free Xilinx ISE webpack tools(14.7).
  • Make a user constrains file(UCF) that maps logic signals to the IO pins.
  • Upload to FPGA flash rom via USB cable.

NOTE: This work flow is just for learning purposes. Actual work flows for FPGA  designs replace work flow 1 and 2 with:

  1. High level system modeling
  2. Low level system modeling
  3. System behavioral description
  1. Form the comparator truth table

We form a digital comparator truth table below:


2. Derive SOP and POS equations

We can form a digital relation from a truth table by 2 ways:

  • Sum of products form(SOP)
  • Products of sum form(POS)

How to do so outside the scope of the tutorial but can be found here.

Taking “i1” and “i2” as inputs 1 and 2 respectively into the comparator/FPGA.

Sum of products form logic

output(eq)= ((~i1)&(~i2)) | (i1&i2)


product of sums form logic

output(eq)= ((~i1)|(i2)) & ((i1)|(~i2))


In an FPGA, the logic is separate from the IO pins. You have to tell the FPGA from which pin should a signal come from. This is important if we want the FPGA to interact with the real world. This is the nature of the versatility of the FPGA though this may seem cumbersome to beginners at first.

NOTE: By saying interacting with the real world, The FPGA is a digital only ready device thus lacks a means of analog to digital conversion without an external ADC via a communication protocol.



  1. Verilog in one day blog link: Asic-world blog
  2. Numato Elbert V2 documentation: Numato elbert V2 documentation
  3. Amazon book link: Digital design and computer architecture, second edition. p55